Altera JESD204B IP - Manual (Page 72)

Signal Width Direction Description
csr_tx_testmode[] 4 Output Indicates the address space that is reserved for
DLL testing within the JESD204B IP core.
• 0—reserved for the IP core.
• 1—program different tests in the transport
layer.
Refer to
csr_tx_testmode
register.
csr_tx_testpattern_
a[]
32 Output A 32-bit fixed data pattern for the test
mode. (23)
csr_tx_testpattern_
b[]
32 Output A 32-bit fixed data pattern for the test
mode. (23)
csr_tx_testpattern_
c[]
32 Output A 32-bit fixed data pattern for the test
mode. (23)
csr_tx_testpattern_
d[]
32 Output A 32-bit fixed data pattern for the test
mode. (23)
Signal Width Direction Description
Out-of-band (OOB)
jesd204_tx_int 1 Output Interrupt pin for the JESD204B IP core.
Interrupt is asserted when any error or
synchronization request is detected. Configure
the
tx_err_enable
register to set the type of
error that can trigger an interrupt.
Signal Width Direction Description
Debug or Testing
jesd204_tx_dlb_
data[]
L*32 Output Optional signal for parallel data from the DLL
in TX to RX loopback testing. (24)
jesd204_tx_dlb_
kchar_data[]
L*4 Output Optional signal to indicate the K character
value for each byte in TX to RX loopback
testing. (24)
(23) You can use this signal in the transport layer to configure programmable test pattern.
(24) This signal is only for internal testing purposes. You can leave this signal disconnected.
UG-01142
2015.05.04
Transmitter 4-35
JESD204B IP Core Functional Description Altera Corporation
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