NXP Semiconductors LPC24XX UM10237 - Manual (Page 102)

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User manual Rev. 04 — 26 August 2009 102 of 792
NXP Semiconductors
UM10237
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail buffer captures the line to which
such a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch Trail buffer. When a branch outside the contents of the
prefetch and Branch Trail buffer is taken, a stall of several clocks is needed to load the
Branch Trail buffer. Subsequently, there will typically be no further instruction fetch delays
until a new and different branch occurs.
If an attempt is made to write directly to the Flash memory, without using the normal Flash
programming interface, the MAM generates a data abort.
4. Memory Acceleration Module blocks
The Memory Accelerator Module is divided into several functional blocks:
• A Flash Address Latch and an incrementor function to form prefetch addresses
• A 128 bit prefetch buffer and an associated Address latch and comparator
• A 128 bit Branch Trail buffer and an associated Address latch and comparator
• A 128 bit Data buffer and an associated Address latch and comparator
• Control logic
• Wait logic
Figure 6–20 shows a simplified block diagram of the Memory Accelerator Module data
paths.
In the following descriptions, the term “fetch” applies to an explicit Flash read request from
the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.
4.1 Flash memory bank
There is one bank of Flash memory for the LPC2400 MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.