NXP Semiconductors LPC24XX UM10237 - Manual (Page 640)

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User manual Rev. 04 — 26 August 2009 640 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
6.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and
PWM1TCR 0xE001 8004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in
Table 25–559 .
9 PWMMR5 Interrupt Interrupt flag for PWM match channel 5. 0
10 PWMMR6 Interrupt Interrupt flag for PWM match channel 6. 0
15:11 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address
0xE001 8000) bit description
Bit Symbol Description Reset
Value
Table 559: PWM Timer Control Register (PWM0TCR - address 0xE001 4004 PWM1TCR address 0xE001 8004) bit
description
Bit Symbol Value Description Reset
Value
0 Counter Enable 1 The PWM Timer Counter and PWM Prescale Counter are
enabled for counting. 0
0 The counters are disabled.
1 Counter Reset 1 The PWM Timer Counter and the PWM Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until this bit is returned to zero. 0
0 Clear reset.
2 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
3 PWM Enable 1 PWM mode is enabled (counter resets to 1). PWM mode
causes the shadow registers to operate in connection with
the Match registers. A program write to a Match register will
not have an effect on the Match result until the
corresponding bit in PWMLER has been set, followed by the
occurrence of a PWM Match 0 event. Note that the PWM
Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being
enabled. Otherwise a Match event will not occur to cause
shadow register contents to become effective. 0
0 Timer mode is enabled (counter resets to 0).
4 Master Disable
(PWM0 only) The two PWMs may be synchronized using the Master
Disable control bit. The Master disable bit of the Master
PWM (PWM0 module) controls a secondary enable input to
both PWMs, as shown in
Figure 25–132 .
This bit has no function in the Slave PWM (PWM1).
0
1 PWM0 is the master, and both PWMs are enabled for
counting.
0 The PWM’s are used independently, and the individual
Counter Enable bits are used to control the PWM’s.
7:5 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA