Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 20 August 2009

115 of 792

NXP Semiconductors

UM10237

Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)

3.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to

27C)

These registers select a priority level for the 32 vectored IRQs. There are 16 priority
levels, corresponding to the values 0 through 15 decimal, of which 15 is the lowest priority.
The reset value of these registers defaults all interrupt to the lowest priority, allowing a
single write to elevate the priority of an individual interrupt.

3.11 Vector Address Register (VICAddress - 0xFFFF FF00)

When an IRQ interrupt occurs, the address of the Interrupt Service Routine (ISR) for the
interrupt that is to be serviced can be read from this register. The address supplied is from
one of the Vector Address Registers (VICVectAddr0-31).

3.12 Software Priority Mask Register (VICSWPriorityMask - 0xFFFF F024)

The Software Priority Mask Register contains individual mask bits for the 16 interrupt
priority levels.

Table 111. Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to

0xFFFF F17C) bit description

Bit

Symbol

Description

Reset value

31:0 VICVectAddr The VIC provides the contents of one of these registers in

response to a read of the Vector Address register (VICAddress
see

Section 7–3.9

). The contents of the specific VICVectAddr

register (one of the 32 VICVectAddr registers) that
corresponds to the interrupt that is to be serviced is read from
VICAddress whenever an interrupt occurs.

0x0000 0000

Table 112. Vector Priority registers 0-31 (VICVectPriority0-31 - addresses 0xFFFF F200 to

0xFFFF F27C) bit description

Bit

Symbol

Description

Reset
value

3:0

VICVectPriority Selects one of 16 priority levels for the corresponding vectored

interrupt.

0xF

31:4 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Table 113. Vector Address register (VICAddress - address 0xFFFF FF00) bit description

Bit

Symbol

Description

Reset
value

31:0 VICAddress Contains the address of the ISR for the currently active interrupt. This

register must be written (with any value) at the end of an ISR, to
update the VIC priority hardware. Writing to the register at any other
time can cause incorrect operation.

0

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