NXP Semiconductors LPC24XX UM10237 - Manual (Page 32)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 32 of 792
NXP Semiconductors
UM10237
Chapter 3: LPC24XX System control
On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog
reset), the following two sequences start simultaneously:
1. After IRC-start-up time (maximum of 60
μs on power-up), IRC provides stable clock
output, the reset signal is latched and synchronized on the IRC clock. The 2-bit IRC
wakeup timer starts counting when the synchronized reset is de-asserted. The boot
code in the ROM starts when the 2-bit IRC wakeup timer times out. The boot code
performs the boot tasks and may jump to the flash. If the flash is not ready to access,
the MAM will insert wait cycles until the flash is ready.
2. After IRC-start-up time (maximum of 60
μs on power-up), IRC provides stable clock
output, the reset signal is synchronized on the IRC clock. The flash wakeup-timer
(9-bit) starts counting when the synchronized reset is de-asserted. The flash
wakeup-timer generates the 100
μs flash start-up time. Once it times out, the flash
initialization sequence is started, which takes about 250 cycles. When it’s done, the
MAM will be granted access to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 3–11 shows an example of the relationship between the RESET, the IRC, and the
processor status when the LPC2400 starts up after reset. For the start-up sequence of the
main oscillator if enabled by the user code, see
Section 4–2.2 “Main oscillator” .
Fig 10. Reset block diagram including the wakeup timer
C
Q
S
APB read of
PDBIT
in PCON
power-
down
C
Q
S
F
OSC
to other
blocks
WAKEUP TIMER
watchdog
reset
external
reset
START
COUNT 2 n
internal RC
oscillator
Reset to the
on-chip circuitry
Reset to
PCON.PD
write “1”
from APB
reset
EINT0 wakeup
EINT1 wakeup
EINT2 wakeup
POR
BOD
EINT3 wakeup
RTC wakeup
BOD wakeup
Ethernet MAC wakeup
USB need_clk wakeup
CAN wakeup
GPIO0 port wakeup
GPIO2 port wakeup