NXP Semiconductors LPC24XX UM10237 - Manual (Page 741)

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User manual Rev. 04 — 26 August 2009 741 of 792
NXP Semiconductors
UM10237
Chapter 33: LPC24XX EmbeddedICE
trigger on an access to a peripheral and the second to trigger on the code segment
that performs the task switching. Therefore when the breakpoints trigger the
information regarding which task has switched out will be ready for examination.
• The watchpoints can be configured such that a range of addresses are enabled for
the watchpoints to be active. The RANGE function allows the breakpoints to be
combined such that a breakpoint is to occur if an access occurs in the bottom
256 bytes of memory but not in the bottom 32 bytes.
The ARM7TDMI-S core has a Debug Communication Channel function in-built. The
debug communication channel allows a program running on the target to communicate
with the host debugger or another separate host without stopping the program flow or
even entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
• For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and
Boundary Scan Architecture.
4. Pin description
[1] This pin has a built-in pull-up resistor.
[2] This pin has no built-in pull-up and no built-in pull-down resistor.
Table 677. EmbeddedICE pin description
Pin Name Type Description
DBGEN [1] Input Debug Enable . JTAG interface control signal (see Section 33–5 ).
TMS [1] Input Test Mode Select. The TMS pin selects the next state in the TAP state
machine.
TCK [2] Input Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It
is a positive edgetriggered clock with the TMS and TCK signals that
define the internal state of the device.
Remark: This clock must be slower than 1
⁄6 of the CPU clock (CCLK) for
the JTAG interface to operate.
TDI [1] Input Test Data In. This is the serial data input for the shift register.
TDO [2] Output Test Data Output. This is the serial data output from the shift register.
Data is shifted out of the device on the negative edge of the TCK signal.
nTRST [1] Input Test Reset. The nTRST pin can be used to reset the test logic within the
EmbeddedICE logic.
RTCK [1] Output Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)"
.
Board designers may need to connect a weak bias resistor to this pin as
described below.