NXP Semiconductors LPC24XX UM10237 - Manual (Page 300)

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User manual Rev. 04 — 26 August 2009 300 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values
from the gray scaler are concurrently shifted into the respective registers. When enough
data is available, a byte is constructed by multiplexing the registered data to the correct bit
position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte
FIFO, which has enough space to store eight color pixels.
6.8 Panel clock generator
The output of the panel clock generator block is the panel clock, pin LCDDCLK. The panel
clock can be based on either the peripheral clock for the LCD block or the external clock
input for the LCD, pin LCDCLKIN. Whichever source is selected can be divided down in
order to produce the internal LCD clock, LCDCLK.
The panel clock generator can be programmed to output the LCD panel clock in the range
of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used.
The CLKSEL bit in the LCD_POL register determines whether the base clock used is
CCLK or the LCDCLKIN pin.
6.9 Timing controller
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides the panel bias and enable signals. These timings are
all register-programmable.
6.10 STN and TFT data select
Support is provided for passive Super Twisted Nematic (STN) and active Thin Film
Transistor (TFT) LCD display types:
6.10.1 STN displays
STN display panels require algorithmic pixel pattern generation to provide pseudo gray
scaling on monochrome displays, or color creation on color displays.
6.10.2 TFT displays
TFT display panels require the digital color value of each pixel to be applied to the display
data inputs.
6.11 Interrupt generation
Four interrupts are generated by the LCD controller, and a single combined interrupt. The
four interrupts are:
• Master bus error interrupt.
• Vertical compare interrupt.
Table 258. Color display driven with 2 2/3 pixel data
Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0]
0 P2[Green] P2[Red] P1[Blue] P1[Green] P1[Red] P0[Blue] P0[Green] P0[Red]
1 P5[Red] P4q[Blue] P4[Green] P4[Red] P3[Blue] P3[Green] P3[Red] P2[Blue]
2 P7[Blue] P7[Green] P7[Red] P6[Blue] P6[Green] P6[Red] P5[Blue] P5[Green]