NXP Semiconductors LPC24XX UM10237 - Manual (Page 502)

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User manual Rev. 04 — 26 August 2009 502 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
15.3 Standard Frame Individual Start Address Register (SFF_sa -
0xE003 C004)
[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
15.4 Standard Frame Group Start Address Register (SFF_GRP_sa -
0xE003 C008)
[1] Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Table 444. Standard Frame Individual Start Address Register (SFF_sa - address
0xE003 C004) bit description
Bit Symbol Description Reset
Value
1:0 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
10:2 SFF_sa [1] The start address of the table of individual Standard Identifiers in AF
Lookup RAM. If the table is empty, write the same value in this register
and the SFF_GRP_sa register described below. For compatibility with
possible future devices, write zeroes in bits 31:11 and 1:0 of this
register. If the eFCAN bit in the AFMR is 1, this value also indicates the
size of the table of Standard IDs which the Acceptance Filter will search
and (if found) automatically store received messages in Acceptance
Filter RAM. 0
31:11 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 445. Standard Frame Group Start Address Register (SFF_GRP_sa - address
0xE003 C008) bit description
Bit Symbol Description Reset
Value
1:0 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA
11:2 SFF_GRP_sa [1] The start address of the table of grouped Standard Identifiers in
AF Lookup RAM. If the table is empty, write the same value in
this register and the EFF_sa register described below. The
largest value that should be written to this register is 0x800, when
only the Standard Individual table is used, and the last word
(address 0x7FC) in AF Lookup Table RAM is used. For
compatibility with possible future devices, please write zeroes in
bits 31:12 and 1:0 of this register. 0
31:12 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA