NXP Semiconductors LPC24XX UM10237 - Manual (Page 78)

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User manual Rev. 04 — 26 August 2009 78 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
[1] The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.
10.2 EMC Status register (EMCStatus - 0xFFE0 8004)
The read-only EMCStatus register provides EMC status information. Table 5–69 shows
the bit assignments for the EMCStatus register.
2 Low-power mode
(L) Indicates normal, or low-power mode: 0
0 Normal mode (warm reset value).
1 Low-power mode.
Entering low-power mode reduces memory controller
power consumption. Dynamic memory is refreshed as
necessary. The memory controller returns to normal
functional mode by clearing the low-power mode bit
(L), or by POR.
This bit must only be modified when the EMC is in idle
state.
[1]
31:3 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined. NA
Table 68. EMC Control register (EMCControl - address 0xFFE0 8000) bit description
Bit Symbol Value Description Reset
Value
Table 69. EMC Status register (EMCStatus - address 0xFFE0 8008) bit description
Bit Symbol Value Description Reset
Value
0 Busy (B) This bit is used to ensure that the memory controller
enters the low-power or disabled mode cleanly by
determining if the memory controller is busy or not: 1
0 EMC is idle (warm reset value).
1 EMC is busy performing memory transactions,
commands, auto-refresh cycles, or is in self-refresh
mode (POR reset value).
1 Write buffer
status (S) This bit enables the EMC to enter low-power mode
or disabled mode cleanly: 0
0 Write buffers empty (POR reset value)
1 Write buffers contain data.
2 Self-refresh
acknowledge
(SA) This bit indicates the operating mode of the EMC: 1
0 Normal mode
1 Self-refresh mode (POR reset value).
31:3 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined. NA