NXP Semiconductors LPC24XX UM10237 - Manual (Page 305)

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User manual Rev. 04 — 26 August 2009 305 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.2.1 Horizontal timing restrictions
DMA requests new data at the start of a horizontal display line. Some time must be
allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD
interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2.
Single panel mode:
• HSW = 3 pixel clock cycles
• HBP = 5 pixel clock cycles
• HFP = 5 pixel clock cycles
• Panel Clock Divisor (PCD) = 1 (LCDCLK / 3)
Dual panel mode:
• HSW = 3 pixel clock cycles
• HBP = 5 pixel clock cycles
• HFP = 5 pixel clock cycles
Table 261. Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)
Bits Function Description Reset
value
31:24 HBP Horizontal back porch.
The 8-bit HBP field is used to specify the number of pixel clock
periods inserted at the beginning of each line or row of pixels.
After the line clock for the previous line has been deasserted, the
value in HBP counts the number of pixel clocks to wait before
starting the next display line. HBP can generate a delay of 1-256
pixel clock cycles. Program with desired value minus 1.
0x0
23:16 HFP Horizontal front porch.
The 8-bit HFP field sets the number of pixel clock intervals at the
end of each line or row of pixels, before the LCD line clock is
pulsed. When a complete line of pixels is transmitted to the LCD
driver, the value in HFP counts the number of pixel clocks to wait
before asserting the line clock. HFP can generate a period of
1-256 pixel clock cycles. Program with desired value minus 1.
0x0
15:8 HSW Horizontal synchronization pulse width.
The 8-bit HSW field specifies the pulse width of the line clock in
passive mode, or the horizontal synchronization pulse in active
mode. Program with desired value minus 1.
0x0
7:2 PPL Pixels-per-line.
The PPL bit field specifies the number of pixels in each line or
row of the screen. PPL is a 6-bit value that represents between
16 and 1024 pixels per line. PPL counts the number of pixel
clocks that occur before the HFP is applied.
Program the value required divided by 16, minus 1. Actual
pixels-per-line = 16 * (PPL + 1). For example, to obtain 320
pixels per line, program PPL as (320/16) -1 = 19.
0x0
1:0 reserved Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -