NXP Semiconductors LPC24XX UM10237 - Manual (Page 21)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 21 of 792
NXP Semiconductors
UM10237
Chapter 2: LPC24XX Memory mapping
4. APB peripheral addresses
The following table shows the APB address map. No APB peripheral uses all of the 16 kB
space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple
locations within each 16 kB range.
Table 17. APB peripherals and base addresses
APB Peripheral Base Address Peripheral Name
0 0xE000 0000 Watchdog Timer
1 0xE000 4000 Timer 0
2 0xE000 8000 Timer 1
3 0xE000 C000 UART0
4 0xE001 0000 UART1
5 0xE001 4000 PWM0
6 0xE001 8000 PWM1
7 0xE001 C000 I 2 C0
8 0xE002 0000 SPI
9 0xE002 4000 RTC
10 0xE002 8000 GPIO
11 0xE002 C000 Pin Connect Block
12 0xE003 0000 SSP1
13 0xE003 4000 ADC
14 0xE003 8000 CAN Acceptance Filter RAM
15 0xE003 C000 CAN Acceptance Filter Registers
16 0xE004 0000 CAN Common Registers
17 0xE004 4000 CAN Controller 1
18 0xE004 8000 CAN Controller 2
19 to 22 0xE004 C000 to 0xE005 8000 Not used
23 0xE005 C000 I 2 C1
24 0xE006 0000 Not used
25 0xE006 4000 Not used
26 0xE006 8000 SSP0
27 0xE006 C000 DAC
28 0xE007 0000 Timer 2
29 0xE007 4000 Timer 3
30 0xE007 8000 UART2
31 0xE007 C000 UART3
32 0xE008 0000 I 2 C2
33 0xE008 4000 Battery RAM
34 0xE008 8000 I 2 S
35 0xE008 C000 SD/MMC Card Interface
36 to 126 0xE009 0000 to 0xE01F BFFF Not used
127 0xE01F C000 System Control Block