NXP Semiconductors LPC24XX UM10237 - Manual (Page 371)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 371 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
When an OUT packet sent by the host has been received successfully, an internal
hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by
returning a NAK. When the device software has read the data, it should free the buffer by
issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the
buffer is cleared, new packets will be accepted.
When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and
again check the status of the PO bit.
See Section 13–13 “Slave mode operation” for a description of when this command is
used.
11.14 Validate Buffer (Command: 0xFA, Data: none)
When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
5 DA Disabled endpoint bit. 0
0 The endpoint is enabled.
1 The endpoint is disabled.
6 RF_MO Rate Feedback Mode. 0
0 Interrupt endpoint is in the Toggle mode.
1 Interrupt endpoint is in the Rate Feedback mode. This means
that transfer takes place without data toggle bit.
7 CND_ST Conditional Stall bit. 0
0 Unstalls both control endpoints.
1 Stall both control endpoints, unless the STP bit is set in the
Select Endpoint register. It is defined only for control OUT
endpoints.
Table 355. Set Endpoint Status Register bit description
Bit Symbol Value Description Reset
value
Table 356. Clear Buffer Register bit description
Bit Symbol Value Description Reset
value
0 PO Packet over-written bit. This bit is only applicable to the control
endpoint EP0. 0
0 The previously received packet is intact.
1 The previously received packet was over-written by a later SETUP
packet.
7:1 - - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA