NXP Semiconductors LPC24XX UM10237 - Manual (Page 57)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 57 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
6. Enable the PLL with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
this before connecting the PLL.
8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register,
or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is
slow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
9. Connect the PLL with one feed sequence.
It's very important not to merge any steps above. For example, don't update the PLLCFG
and enable the PLL simultaneously with the same feed sequence.
3.3 Clock dividers
The output of the PLL must be divided down for use by the CPU and the USB block.
Separate dividers are provided such that the CPU frequency can be determined
independently from the USB block, which always requires 48 MHz with a 50% duty cycle
for proper operation (see
Figure 4–12 ).
3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104)
The CCLKCFG register controls the division of the PLL output before it is used by the
CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the
output must be divided in order to bring the CPU clock frequency (cclk) within operating
limits. An 8 bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off the PLL.
Note: When the USB interface is used in an application, cclk must be at least 18 MHz in
order to support internal operations of the USB block.
The cclk is derived from the PLL output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL output, etc..
Table 53. CPU Clock Configuration register (CCLKCFG - address 0xE01F C104) bit
description
Bit Symbol Description Reset
value
7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) from the
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.
0x00