NXP Semiconductors LPC24XX UM10237 - Manual (Page 604)

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User manual Rev. 04 — 26 August 2009 604 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit
10.4 I 2 C interrupt routine
Determine the I 2 C state and which state routine will be used to handle it.
1. Read the I 2 C status from I2STA.
2. Use the status value to branch to one of 26 possible state routines.
10.5 Non mode specific states
10.5.1 State : 0x00
Bus Error. Enter not addressed Slave mode and release bus.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit
10.6 Master states
State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W
bit decides whether the next state is within Master Transmit mode or Master Receive
mode.
10.6.1 State : 0x08
A Start condition has been transmitted. The Slave Address + R/W bit will be transmitted,
an ACK bit will be received.
1. Write Slave Address with R/W bit to I2DAT.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
5. Set up Master Receive mode data buffer.
6. Initialize Master data counter.
7. Exit
10.6.2 State : 0x10
A repeated Start condition has been transmitted. The Slave Address + R/W bit will be
transmitted, an ACK bit will be received.
1. Write Slave Address with R/W bit to I2DAT.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.