NXP Semiconductors LPC24XX UM10237 - Manual (Page 712)

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User manual Rev. 04 — 26 August 2009 712 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
• Supports 8, 16, and 32 bit wide transactions.
• Big-endian and little-endian support. The GPDMA defaults to little-endian mode on
reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
• Test registers for use in block and integration system level testing.
• Identification registers that uniquely identify the GPDMA. These can be used by an
operating system to automatically configure itself.
4. Functional overview
This chapter describes the major functional blocks of the GPDMA. It contains the following
sections:
• GPDMA functional description
• System considerations
• System connectivity
• Use with memory management unit based systems
4.1 Memory regions accessible by the GPDMA
[1] For LPC2458, see Table 2–14 .
4.2 GPDMA functional description
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
Table 649. GPDMA accessible memory [1]
Memory region Address range Memory Type
On-chip RAM 0x7FD0 0000 - 0x7FD0 3FFF USB RAM (16 kB)
Off-Chip Memory Four static memory banks, 16 MB each
0x8000 0000 - 0x80FF FFFF Static memory bank 0
0x8100 0000 - 0x81FF FFFF Static memory bank 1
0x8200 0000 - 0x82FF FFFF Static memory bank 2
0x8300 0000 - 0x83FF FFFF Static memory bank 3
Four dynamic memory banks, 256 MB each
0xA000 0000 - 0xAFFF FFFF Dynamic memory bank 0
0xB000 0000 - 0xBFFF FFFF Dynamic memory bank 1
0xC000 0000 - 0xCFFF FFFF Dynamic memory bank 2
0xD000 0000 - 0xDFFF FFFF Dynamic memory bank 3