NXP Semiconductors LPC24XX UM10237 - Manual (Page 80)

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User manual Rev. 04 — 26 August 2009 80 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
[1] Clock enable must be HIGH during SDRAM initialization.
[2] The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
[3] Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
2 Self-refresh
request,
EMCSREFREQ
(SR) 0 Normal mode. 1
1 Enter self-refresh mode (POR reset value).
By writing 1 to this bit self-refresh can be entered under
software control. Writing 0 to this bit returns the EMC to
normal mode.
The self-refresh acknowledge bit in the EMCStatus
register must be polled to discover the current operating
mode of the EMC.
[2]
4:3 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
5 Memory clock
control (MMC) 0 CLKOUT enabled (POR reset value). 0
1 CLKOUT disabled. [3]
6 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
8:7 SDRAM
initialization (I) 00 Issue SDRAM NORMAL operation command (POR
reset value). 00
01 Issue SDRAM MODE command.
10 Issue SDRAM PALL (precharge all) command.
11 Issue SDRAM NOP (no operation) command)
12:9 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
13 Low-power
SDRAM
deep-sleep
mode (DP) 0 Normal operation (POR reset value). 0
1 Enter Deep-sleep mode.
31:14 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 71. Dynamic Control register (EMCDynamicControl - address 0xFFE0 8020) bit
description
Bit Symbol Value Description Reset
Value