NXP Semiconductors LPC24XX UM10237 - Manual (Page 94)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 94 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
Table 5–90 shows the bit assignments for the EMCStaticWaitWen0-3 registers.
10.23 Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3 -
0xFFE0 8208, 228, 248, 268)
The EMCStaticWaitOen0-3 registers enable you to program the delay from the chip select
or address change, whichever is later, to the output enable. It is recommended that these
registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Table 5–91 shows the bit assignments for the EMCStaticWaitOen0-3 registers.
10.24 Static Memory Read Delay registers (EMCStaticWaitRd0-3 -
0xFFE0 820C, 22C, 24C, 26C)
The EMCStaticWaitRd0-3 registers enable you to program the delay from the chip select
to the read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the EMCStaticConfig0-3 registers. These
registers are accessed with one wait state.
Table 5–92 shows the bit assignments for the EMCStaticWaitRd0-3 registers.
Table 90. Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - address
0xFFE0 8204,0xFFE0 8224, 0xFFE0 8244, 0xFFE0 8264) bit description
Bit Symbol Value Description Reset
Value
3:0 Wait write
enable
(WAITWEN) Delay from chip select assertion to write enable. 0x0
0x0 One CCLK cycle delay between assertion of chip select
and write enable (POR reset value).
0x1 - 0xF (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x
tCCLK.
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 91. Static Memory Output Enable delay registers (EMCStaticWaitOen03 - address
0xFFE0 8208, 0xFFE0 8228, 0xFFE0 8248, 0xFFE0 8268) bit description
Bit Symbol Value Description Reset
Value
3:0 Wait output
enable
(WAITOEN) Delay from chip select assertion to output enable. 0x0
0x0 No delay (POR reset value).
0x1 -
0xF n cycle delay. The delay is WAITOEN x tCCLK.
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA