NXP Semiconductors LPC24XX UM10237 - Manual (Page 669)

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User manual Rev. 04 — 26 August 2009 669 of 792
NXP Semiconductors
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
5.1 A/D Control Register (AD0CR - 0xE003 4000)
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
AD0DR3 A/D Channel 3 Data Register. This register
contains the result of the most recent
conversion completed on channel 3. R/W NA 0xE003 401C
AD0DR4 A/D Channel 4 Data Register. This register
contains the result of the most recent
conversion completed on channel 4. R/W NA 0xE003 4020
AD0DR5 A/D Channel 5 Data Register. This register
contains the result of the most recent
conversion completed on channel 5. R/W NA 0xE003 4024
AD0DR6 A/D Channel 6 Data Register. This register
contains the result of the most recent
conversion completed on channel 6. R/W NA 0xE003 4028
AD0DR7 A/D Channel 7 Data Register. This register
contains the result of the most recent
conversion completed on channel 7. R/W NA 0xE003 402C
Table 592. Summary of ADC registers
Name Description Access Reset
Value [1]
Address
Table 593: A/D Control Register (AD0CR - address 0xE003 4000) bit description
Bit Symbol Value Description Reset
Value
7:0 SEL Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0
selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of
these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All
zeroes is equivalent to 0x01. 0x01
15:8 CLKDIV The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D
converter, which should be less than or equal to 4.5 MHz. Typically, software should
program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in
certain cases (such as a high-impedance analog source) a slower clock may be
desirable. 0
16 BURST 0 Conversions are software controlled and require 11 clocks. 0
1 The AD converter does repeated conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that’s in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.