NXP Semiconductors LPC24XX UM10237 - Manual (Page 48)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 48 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
3.2.2 PLL and startup/boot code interaction
The boot code for the LPC2400 is a different from previous NXP ARM7 LPC2000 chips.
When there is no valid code (determined by the checksum word) in the user flash or the
ISP enable pin (P2.10) is pulled low on startup, the ISP mode will be entered and the boot
code will setup the PLL with the IRC. Therefore it can not be assumed that the PLL is
disabled when the user opens a debug session to debug the application code. The user
startup code must follow the steps described in this chapter to disconnect the PLL.
The boot code may also change the values for some registers when the chip enters ISP
mode. For example, the GPIOM bit in the SCS register is set in the ISP mode. If the user
doesn't notice it and clears the GPIOM bit in the application code, the application code will
not be able to operate with the traditional GPIO function on PORT0 and PORT1.
3.2.3 PLL register description
The PLL is controlled by the registers shown in Table 4–43 . More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of PLL values may result in incorrect operation of the
device!
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
3.2.4 PLL Control register (PLLCON - 0xE01F C080)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
Table 43. PLL registers
Name Description Access Reset
value [1]
Address
PLLCON PLL Control Register. Holding register for
updating PLL control bits. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place. R/W 0 0xE01F C080
PLLCFG PLL Configuration Register. Holding register for
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place. R/W 0 0xE01F C084
PLLSTAT PLL Status Register. Read-back register for
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the PLL status. RO 0 0xE01F C088
PLLFEED PLL Feed Register. This register enables
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation. WO NA 0xE01F C08C