NXP Semiconductors LPC24XX UM10237 - Manual (Page 60)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 60 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
[1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.
3.4 Power control
The LPC2400 supports a variety of power control features. There are four special modes
of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application.
The LPC2400 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock and a
small static RAM, referred to as the Battery RAM. This feature is described in more detail
later in this chapter under the heading Power Domains, and in the Real Time Clock and
Battery RAM chapter.
3.4.1 Idle mode
When Idle mode is entered, the clock to the core is stopped. Resumption from the Idle
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
3.4.2 Sleep mode
When the chip enters the Sleep mode, the main oscillator is powered down and all clocks
are stopped. The output of the IRC is disabled but the IRC is not powered down for a fast
wakeup later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may
be used as the wakeup source. The flash is left in the standby mode allowing a very quick
wakeup. The PLL is automatically turned off and disconnected. The CCLK and USBCLK
clock dividers automatically get reset to zero.
Table 58. Peripheral Clock Selection register bit values
PCLKSEL0 and PCLKSEL1
individual peripheral’s clock
select options Function Reset
value
00 PCLK_xyz = CCLK/4 00
01 PCLK_xyz = CCLK [1]
10 PCLK_xyz = CCLK/2
11 Peripheral’s clock is selected to PCLK_xyz = CCLK/8
except for CAN1, CAN2, and CAN filtering when ’11’
selects PCLK_xyz = CCLK/6.