NXP Semiconductors LPC24XX UM10237 - Manual (Page 405)

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User manual Rev. 04 — 26 August 2009 405 of 792
NXP Semiconductors
UM10237
Chapter 15: LPC24XX USB OTG controller
7.9 OTG Clock Status Register (OTGClkSt - 0xFFE0 CFF8)
This register holds the clock availability status. When enabling a clock via OTGClkCtrl,
software should poll the corresponding bit in this register. If it is set, then software can go
ahead with the register access. Software does not have to repeat this exercise for every
access, provided that the OTGClkCtrl bits are not disturbed.
1 DEV_CLK_EN Device clock enable 0
0 Disable the Device clock.
1 Enable the Device clock.
2 I2C_CLK_EN I2C clock enable 0
0 Disable the I 2 C clock.
1 Enable the I 2 C clock.
3 OTG_CLK_EN OTG clock enable 0
0 Disable the OTG clock.
1 Enable the OTG clock.
4 AHB_CLK_EN AHB master clock enable 0
0 Disable the AHB clock.
1 Enable the AHB clock.
31:5 - NA Reserved, user software should not write ones
to reserved bits. The value read from a
reserved bit is not defined. NA
Table 368. OTG_clock_control register (OTG_clock_control - address 0xFFE0 CFF4) bit
description
Bit Symbol Value Description Reset
Value
Table 369. OTG_clock_status register (OTGClkSt - address 0xFFE0 CFF8) bit description
Bit Symbol Value Description Reset
Value
0 HOST_CLK_ON Host clock status. 0
0 Host clock is not available.
1 Host clock is available.
1 DEV_CLK_ON Device clock status. 0
0 Device clock is not available.
1 Device clock is available.
2 I2C_CLK_ON I2C clock status. 0
0 I2C clock is not available.
1 I2C clock is available.
3 OTG_CLK_ON OTG clock status. 0
0 OTG clock is not available.
1 OTG clock is available.