NXP Semiconductors LPC24XX UM10237 - Manual (Page 633)

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User manual Rev. 04 — 26 August 2009 633 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
3. Description
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the microcontroller. The Timer is designed to
count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform
other actions when specified timer values occur, based on seven match registers. It also
includes four capture inputs to save the timer value when an input signal transitions, and
optionally generate an interrupt when those events occur. The PWM function is in addition
to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
Figure 25–132 shows the block diagram of the PWM. The portions that have been added
to the standard timer block are on the right hand side and at the top of the diagram. At the
lower left of the diagram may be found the Master Enable output from the Timer Control
register that allows the Master PWM (PWM0) to enable both itself and the Salve PWM
(PWM1) at the same time, if desired. The Master Enable output from PWM0 is connected
to the external enable input of both PWM blocks.