NXP Semiconductors LPC24XX UM10237 - Manual (Page 277)

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User manual Rev. 04 — 26 August 2009 277 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
• RegReset: Resets all of the datapaths and registers in the host registers module,
excluding the registers in the MAC. A soft reset of the registers will also abort all AHB
transactions of the transmit and receive datapath. The reset bit will be cleared
autonomously by the Ethernet block.
To do a full soft reset of the Ethernet block, device driver software must:
• Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
• Set the RegReset bit in the Command register, this bit clears automatically.
• Reinitialize the MAC registers (0x000 to 0x0FC).
• Reset the ‘SOFT RESET’ bit in the MAC1 register to 0.
To reset just the transmit datapath, the device driver software has to:
• Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.
• Disable the Tx DMA managers by setting the TxEnable bits in the Command register
to 0.
• Set the TxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0.
To reset just the receive datapath, the device driver software has to:
• Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1
configuration register and resetting of the RxEnable bit of the Command register.
• Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
• Set the RxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.
9.22 Ethernet errors
The Ethernet block generates errors for the following conditions:
• A reception can cause an error: AlignmentError, RangeError, LengthError,
SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the
receive StatusInfo and in the interrupt status register (IntStatus).
• A transmission can cause an error: LateCollision, ExcessiveCollision,
ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the
transmission StatusInfo and in the interrupt status register (IntStatus).
9.23 AHB bandwidth
The Ethernet block is connected to an AHB bus which must carry all of the data and
control information associated with all Ethernet traffic in addition to the CPU accesses
required to operate the Ethernet block and deal with message contents.
9.23.1 DMA access
Assumptions
By making some assumptions, the bandwidth needed for each type of AHB transfer can
be calculated and added in order to find the overall bandwidth requirement.