NXP Semiconductors LPC24XX UM10237 - Manual (Page 635)

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User manual Rev. 04 — 26 August 2009 635 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
3.1 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle
unless their match value is equal to 0.
2. Each PWM output will go low when its match value is reached. If no match occurs (i.e.
the match value is greater than the PWM rate), the PWM output remains continuously
high.
3.2 Rules for double edge controlled PWM outputs
Five rules are used to determine the next value of a PWM output when a new cycle is
about to begin:
1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time
point which is coincident with the beginning of the next PWM cycle), except as noted
in rule 3.
2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0
value) have the same effect, except as noted in rule 3. For example, a request for a
falling edge at the beginning of the PWM cycle has the same effect as a request for a
falling edge at the end of a PWM cycle.
3. When match values are changing, if one of the "old" match values is equal to the
PWM rate, it is used again once if the neither of the new match values are equal to 0
or the PWM rate, and there was no old match value equal to 0.
4. If both a set and a clear of a PWM output are requested at the same time, clear takes
precedence. This can occur when the set and clear match values are the same as in,
or when the set or clear value equals 0 and the other value equals the PWM rate.
5. If a match value is out of range (i.e. greater than the PWM rate value), no match event
occurs and that match channel has no effect on the output. This means that the PWM
output will remain always in one state, allowing always low, always high, or
"no change" outputs.
3.3 Summary of differences from the standard timer block
1. A synchronizing register (shadow register) is added to each match register to allow
changes to take effect only when requested by software, and only at the transition
between PWM cycles.
2. A new Load Enable Register (LER) is added to allow software to control Match
register updates. The LER contains one bit for each Match register. When a bit in the
LER is written with a one, the shadow register contents for the corresponding Match
channel are loaded into the actual Match register when the counter is reset (when
Match 0 occurs). LER bits are reset automatically when the counter is reset.
3. A single PWM mode bit is added to the TCR register. The PWM mode enables
loading the actual match registers from the shadow registers under
software/hardware control as described above. When PWM mode is not enabled, the
match value shadow registers are either transparent or bypassed.
4. A Master Enable bit is added to the TCR register, the value of which is brought out of
the PWM block. An external enable input is added to the PWM block, that is
connected to the Master Enable output of the Master PWM block.