UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
783 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
5
Modes of operation . . . . . . . . . . . . . . . . . . . . 395
6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . 395
6.1
Connecting port U1 to an external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 396
6.2
Connecting USB as a two-port host . . . . . . . 399
6.3
Connecting USB as one port host and one port
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
7
Register description . . . . . . . . . . . . . . . . . . . 400
7.1
USB Interrupt Status Register (USBIntSt -
0xE01F C1C0) . . . . . . . . . . . . . . . . . . . . . . . 401
7.2
OTG Interrupt Status Register (OTGIntSt -
0xE01F C100) . . . . . . . . . . . . . . . . . . . . . . . 402
7.3
OTG Interrupt Enable Register (OTGIntEn -
0xFFE0 C104) . . . . . . . . . . . . . . . . . . . . . . . 402
7.4
OTG Interrupt Set Register (OTGIntSet -
0xFFE0 C20C) . . . . . . . . . . . . . . . . . . . . . . . 402
7.5
OTG Interrupt Clear Register (OTGIntClr -
0xFFE0 C10C) . . . . . . . . . . . . . . . . . . . . . . . 402
7.6
OTG Status and Control Register (OTGStCtrl -
0xFFE0 C110). . . . . . . . . . . . . . . . . . . . . . . . 402
7.7
OTG Timer Register (OTGTmr -
0xFFE0 C114). . . . . . . . . . . . . . . . . . . . . . . . 404
7.8
OTG Clock Control Register (OTGClkCtrl -
0xFFE0 CFF4) . . . . . . . . . . . . . . . . . . . . . . . 404
7.9
OTG Clock Status Register (OTGClkSt -
0xFFE0 CFF8) . . . . . . . . . . . . . . . . . . . . . . . 405
7.10
I2C Receive Register (I2C_RX -
0xFFE0 C300) . . . . . . . . . . . . . . . . . . . . . . . 406
7.11
I2C Transmit Register (I2C_TX -
0xFFE0 C300) . . . . . . . . . . . . . . . . . . . . . . . 406
7.12
I2C Status Register (I2C_STS -
0xFFE0 C304) . . . . . . . . . . . . . . . . . . . . . . . 406
7.13
I2C Control Register (I2C_CTL -
0xFFE0 C308) . . . . . . . . . . . . . . . . . . . . . . . 408
7.14
I2C Clock High Register (I2C_CLKHI -
0xFFE0 C30C) . . . . . . . . . . . . . . . . . . . . . . . 409
7.15
I2C Clock Low Register (I2C_CLKLO -
0xFFE0 C310) . . . . . . . . . . . . . . . . . . . . . . . 410
7.16
Interrupt handling . . . . . . . . . . . . . . . . . . . . . 410
8
HNP support . . . . . . . . . . . . . . . . . . . . . . . . . . 411
8.1
B-device: peripheral to host switching . . . . . 412
Remove D+ pull-up . . . . . . . . . . . . . . . . . . . . 414
Add D+ pull-up . . . . . . . . . . . . . . . . . . . . . . . . 415
8.2
A-device: host to peripheral HNP switching. 415
Set BDIS_ACON_EN in external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Clear BDIS_ACON_EN in external OTG trans-
ceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Discharge V
BUS
. . . . . . . . . . . . . . . . . . . . . . . 418
Load and enable OTG timer . . . . . . . . . . . . . 419
Stop OTG timer . . . . . . . . . . . . . . . . . . . . . . . 419
Suspend host on port 1 . . . . . . . . . . . . . . . . . 419
9
Clocking and power management . . . . . . . . 419
9.1
Device clock request signals . . . . . . . . . . . . 420
9.1.1
Host clock request signals . . . . . . . . . . . . . . 421
9.2
Power-down mode support . . . . . . . . . . . . . 421
10
USB OTG controller initialization . . . . . . . . 421
Chapter 16: LPC24XX UART0/2/3
1
Basic configuration . . . . . . . . . . . . . . . . . . . . 423
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 423
4
Register description . . . . . . . . . . . . . . . . . . . 424
4.1
UARTn Receiver Buffer Register (U0RBR -
0xE000 C000, U2RBR - 0xE007 8000, U3RBR -
0xE007 C000 when DLAB = 0, Read Only) . 427
4.2
UARTn Transmit Holding Register (U0THR -
0xE000 C000, U2THR - 0xE007 8000, U3THR -
0xE007 C000 when DLAB = 0, Write Only) . 427
4.3
UARTn Divisor Latch LSB Register (U0DLL -
0xE000 C000, U2DLL - 0xE007 8000, U3DLL -
0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM -
0xE000 C004, U2DLL - 0xE007 8004, U3DLL -
0xE007 C004 when DLAB = 1). . . . . . . . . . . 427
4.4
UARTn Interrupt Enable Register (U0IER -
0xE000 C004, U2IER - 0xE007 8004, U3IER -
0xE007 C004 when DLAB = 0). . . . . . . . . . . 428
4.5
UARTn Interrupt Identification Register (U0IIR -
0xE000 C008, U2IIR - 0xE007 8008, U3IIR -
0x7008 C008, Read Only) . . . . . . . . . . . . . . 429
4.6
UARTn FIFO Control Register (U0FCR -
0xE000 C008, U2FCR - 0xE007 8008, U3FCR -
0xE007 C008, Write Only) . . . . . . . . . . . . . . 431
4.7
UARTn Line Control Register (U0LCR -
0xE000 C00C, U2LCR - 0xE007 800C, U3LCR -
0xE007 C00C) . . . . . . . . . . . . . . . . . . . . . . . 431
4.8
UARTn Line Status Register (U0LSR -
0xE000 C014, U2LSR - 0xE007 8014, U3LSR -
0xE007 C014, Read Only) . . . . . . . . . . . . . . 432
4.9
UARTn Scratch Pad Register (U0SCR -
0xE000 C01C, U2SCR - 0xE007 801C U3SCR -
0xE007 C01C) . . . . . . . . . . . . . . . . . . . . . . . 434
4.10
UARTn Auto-baud Control Register (U0ACR -
0xE000 C020, U2ACR - 0xE007 8020, U3ACR -
0xE007 C020) . . . . . . . . . . . . . . . . . . . . . . . 434
4.10.1
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 435
4.10.2
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 435
4.11
IrDA Control Register for UART3 Only (U3ICR -
0xE007 C024) . . . . . . . . . . . . . . . . . . . . . . . 437
4.12
UARTn Fractional Divider Register (U0FDR -
0xE000 C028, U2FDR - 0xE007 8028, U3FDR -
0xE007 C028) . . . . . . . . . . . . . . . . . . . . . . . 437
4.12.1
Baudrate calculation . . . . . . . . . . . . . . . . . . 438
4.12.1.1
Example 1: PCLK = 14.7456 MHz,
BR = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . 440
4.12.1.2
Example 2: PCLK = 12 MHz, BR = 115200 . 440
4.13
UARTn Transmit Enable Register (U0TER -
0xE000 C030, U2TER - 0xE007 8030, U3TER -
0xE007 C030) . . . . . . . . . . . . . . . . . . . . . . . 440