Usb device controller initialization, Section 13–12 – NXP Semiconductors LPC24XX UM10237 User Manual

Page 372

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

372 of 792

NXP Semiconductors

UM10237

Chapter 13: LPC24XX USB device controller

Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.

A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.

See

Section 13–13 “Slave mode operation”

for a description of when this command is

used.

12. USB device controller initialization

The LPC2400 USB device controller initialization includes the following steps:

1. Enable the device controller by setting the PCUSB bit of PCONP.

2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk, and

the desired frequency for cclk. For correct operation of synchronization logic in the
device controller, the minimum cclk frequency is 18 MHz. For the procedure for
determining the PLL setting and configuration, see

Section 4–3.2.12 “Procedure for

determining PLL settings”

.

3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits

in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until
they are set.

4. Select the desired USB port pins using the USBPortSel register. The

PORTSEL_CLK_EN bit must be set in USBClkCtrl before accessing USBPortSel and
should be cleared after accessing USBPortSel.

5. Enable the USB pin functions by writing to the corresponding PINSEL register.

6. Disable the pull-up resistor on the V

BUS

pin using the corresponding PINMODE

register.

7. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the

EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.

8. Enable endpoint interrupts (Slave mode):

Clear all endpoint interrupts using USBEpIntClr.

Clear any device interrupts using USBDevIntClr.

Enable Slave mode for the desired endpoints by setting the corresponding bits in

USBEpIntEn.

Set the priority of each enabled interrupt using USBEpIntPri.

Configure the desired interrupt mode using the SIE Set Mode command.

Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,

and possibly EP_FAST).

9. Configure the DMA (DMA mode):

Disable DMA operation for all endpoints using USBEpDMADis.

Clear any pending DMA requests using USBDMARClr.

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