NXP Semiconductors LPC24XX UM10237 - Manual (Page 719)

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User manual Rev. 04 — 26 August 2009 719 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
5.3 Enabling a DMA channel
To enable the DMA channel set the Channel Enable bit in the relevant DMA channel
Configuration Register (
Section 32–6.2.6 “Channel Configuration Registers
(DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)” ).
Note: The channel must be fully initialized before it is enabled. Additionally, you must set
the Enable bit of the GPDMA before any channels are enabled.
5.4 Disabling a DMA channel
You can disable a DMA channel in the following ways:
• Write directly to the Channel Enable bit. Any outstanding data in the FIFOs is lost if
this method is used.
• Use the Active and Halt bits in conjunction with the Channel Enable bit.
• Wait until the transfer completes. The channel is then automatically disabled.
5.5 Disabling a DMA channel without losing data in the FIFO
To disable a DMA channel without losing data in the FIFO:
1. Set the Halt bit in the relevant channel Configuration Register ( Section 32–6.2.6
“Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130)”
). This causes any further DMA requests to
be ignored.
2. Poll the Active bit in the relevant channel Configuration Register until it reaches 0.
This bit indicates whether there is any data in the channel which has to be transferred.
3. Clear the Channel Enable bit in the relevant channel Configuration Register.
5.6 Setup a new DMA transfer
To set up a new DMA transfer:
1. If the channel is not set aside for the DMA transaction:
– Read the DMACEnbldChns Register and find out which channels are inactive (see
Section 32–6.1.8 “Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)” ).
– Choose an inactive channel that has the required priority.
2. Program the GPDMA.
5.7 Disabling a DMA channel and losing data in the FIFO
Clear the relevant Channel Enable bit in the relevant channel Configuration Register
(
Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration -
0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)” ). The current AHB transfer, if
one is in progress, completes and the channel is disabled. Any data in the FIFO is lost.
5.8 Halting a DMA transfer
Set the Halt bit in the relevant DMA channel Configuration Register. The current source
request is serviced. Any further source DMA requests are ignored until the Halt bit is
cleared.