NXP Semiconductors LPC24XX UM10237 - Manual (Page 306)

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User manual Rev. 04 — 26 August 2009 306 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
• PCD = 5 (LCDCLK / 7)
If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10,
data does not corrupt for PCD = 4, the minimum value.
7.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)
The LCD_TIMV register controls the Vertical Synchronization pulse Width (VSW), the
Vertical Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the
Lines-Per-Panel (LPP).
The contents of the LCD_TIMV register are described in Table 12–262 .
Table 262. Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)
Bits Function Description Reset
value
31:24 VBP Vertical back porch.
This is the number of inactive lines at the start of a frame, after
the vertical synchronization period. The 8-bit VBP field specifies
the number of line clocks inserted at the beginning of each
frame. The VBP count starts immediately after the vertical
synchronization signal for the previous frame has been negated
for active mode, or the extra line clocks have been inserted as
specified by the VSW bit field in passive mode. After this has
occurred, the count value in VBP sets the number of line clock
periods inserted before the next frame. VBP generates 0–255
extra line clock cycles. Program to zero on passive displays for
improved contrast.
0x0