NXP Semiconductors LPC24XX UM10237 - Manual (Page 85)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 85 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR -
0xFFE0 8044)
The EMCDynamicTWR register enables you to program the write recovery time, tWR. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tWR, tDPL, tRWL, or tRDL. This register is accessed with one
wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–79 shows the bit assignments for the EMCDynamicTWR register.
10.13 Dynamic Memory Active to Active Command Period register
(EMCDynamictRC - 0xFFE0 8048)
The EMCDynamicTRC register enables you to program the active to active command
period, tRC. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tRC. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–80 shows the bit assignments for the EMCDynamicTRC register.
Table 78. Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL -
address 0xFFE0 8040) bit description
Bit Symbol Value Description Reset
Value
3:0 Data-in to active
command
(tDAL) 0x0 -
0xE n clock cycles. The delay is in CCLK cycles. 0xF
0xF 15 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 79. Dynamic Memory Write recover Time register (EMCDynamictWR - address
0xFFE0 8044) bit description
Bit Symbol Value Description Reset
Value
3:0 Write recovery
time (tWR) 0x0 -
0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA