NXP Semiconductors LPC24XX UM10237 - Manual (Page 374)

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User manual Rev. 04 — 26 August 2009 374 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
endpoints, the next packet will be received irrespective of whether the buffer has been
cleared. Any data not read from the buffer before the end of the frame is lost. See
Section 13–15 “Double buffered endpoint operation” for more details.
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
13.3 Data transfer for IN endpoints
When writing data to an endpoint buffer, WR_EN ( Section 13–9.6.5 “USB Control register
(USBCtrl - 0xFFE0 C228)” ) is set and software writes to the number of bytes it is going to
send in the packet to the USBTxPLen register ( Section 13–9.6.4 ). It can then write data
continuously in the USBTxData register.
When the the number of bytes programmed in USBTxPLen have been written to
USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt
register. Software issues a Validate Buffer (
Section 13–11.14 “Validate Buffer (Command:
0xFA, Data: none)” ) command. The endpoint is now ready to send the packet. For IN
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
14. DMA operation
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections
Section 13–14.2 “USB device communication area” and Section 13–14.3
“Triggering the DMA engine” . The fields of the DMA Descriptor are described in section
Section 13–14.4 “The DMA descriptor” . The last three sections describe DMA operation:
Section 13–14.5 “Non-isochronous endpoint operation” , Section 13–14.6 “Isochronous
endpoint operation” , and Section 13–14.7 “Auto Length Transfer Extraction (ATLE) mode
operation” .
14.1 Transfer terminology
Within this section three types of transfers are mentioned:
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
(RAM).
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.