NXP Semiconductors LPC24XX UM10237 - Manual (Page 207)

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User manual Rev. 04 — 26 August 2009 207 of 792
NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
6.6 GPIO interrupt registers
The following registers configure the pins of port 0 and port 2 to generate interrupts.
6.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080)
This read-only register indicates the presence of interrupt pending on all of the GPIO ports
that support GPIO interrupts. Only one bit per port is used.
6.6.2 GPIO Interrupt Enable for Rising edge register (IO0IntEnR - 0xE002 8090
and IO2IntEnR - 0xE002 80B0)
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding GPIO port pin.
6.6.3 GPIO Interrupt Enable for Falling edge register (IO0IntEnF - 0xE002 8094
and IO2IntEnF - 0xE002 80B4)
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port pin.
Table 175. GPIO overall Interrupt Status register (IOIntStatus - address 0xE002 8080) bit
description
Bit Symbol Value Description Reset
value
0 P0Int
0
PORT0 GPIO interrupt pending.
There are no pending interrupts on PORT0.
0
1 There is at least one pending interrupt on PORT0.
1 - - Reserved. The value read from a reserved bit is not defined. NA
2 P2Int
0
PORT2 GPIO interrupt pending.
There are no pending interrupts on PORT2.
0
1 There is at least one pending interrupt on PORT2.
31:2 - - Reserved. The value read from a reserved bit is not defined. NA
Table 176. GPIO Interrupt Enable for Rising edge register (IO0IntEnR - address 0xE002 8090
and IO2IntEnR - address 0xE002 80B0) bit description
Bit Symbol Value Description Reset
value
31:0 P0xER
and
P2xER
0
Enable Rising edge. Bit 0 in IOxIntEnR corresponds to pin Px.0,
bit 31 in IOxIntEnR corresponds to pin Px.31.
Rising edge interrupt is disabled on the controlled pin.
0
1 Rising edge interrupt is enabled on the controlled pin.
Table 177. GPIO Interrupt Enable for Falling edge register (IO0IntEnF - address 0xE002 8094
and IO2IntEnF - address 0xE002 80B4) bit description
Bit Symbol Value Description Reset
value
31:0 P0xEF
and
P2xEF
0
Enable Falling edge. Bit 0 in IOxIntEnF corresponds to pin Px.0,
bit 31 in IOxIntEnF corresponds to pin Px.31.
Falling edge interrupt is disabled on the controlled pin.
0
1 Falling edge interrupt is enabled on the controlled pin.