NXP Semiconductors LPC24XX UM10237 - Manual (Page 587)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 587 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
In Figures 120 to 124 , circles are used to indicate when the serial interrupt flag is set. The
numbers in the circles show the status code held in the I2STAT register. At these points, a
service routine must be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended until the serial
interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2STAT is used to branch to
the appropriate service routine. For each status code, the required software action and
details of the following serial transfer are given in tables from
Table 22–525 to
Table 22–529 .
9.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
Figure 22–120 ). Before the master transmitter mode can be entered, I2CON must be
initialized as follows:
The I 2 C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
set to logic 1 to enable the I 2 C block. If the AA bit is reset, the I 2 C block will not
acknowledge its own slave address or the general call address in the event of another
device becoming master of the bus. In other words, if AA is reset, the I
2 C interface cannot
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I 2 C logic will
now test the I 2 C bus and generate a start condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads I2DAT with the
slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in
Table 22–525 . After a repeated start condition (state 0x10). The I 2 C block may switch to
the master receiver mode by loading I2DAT with SLA+R).
A Not acknowledge bit (high level at SDA)
Data 8 bit data byte
P Stop condition
Table 521. Abbreviations used to describe an I 2 C operation
Abbreviation Explanation
Table 522. I2CONSET used to initialize Master Transmitter mode
Bit 7 6 5 4 3 2 1 0
Symbol - I2EN STA STO SI AA - -
Value - 1 0 0 0 x - -