NXP Semiconductors LPC24XX UM10237 - Manual (Page 449)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 449 of 792
NXP Semiconductors
UM10237
Chapter 17: LPC24XX UART1
4.5 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read
Only)
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
7 CTS
Interrupt
Enable If auto-cts mode is enabled this bit enables/disables the
modem status interrupt generation on a CTS1 signal
transition. If auto-cts mode is disabled a CTS1 transition
will generate an interrupt if Modem Status Interrupt Enable
(U1IER[3]) is set.
In normal operation a CTS1 signal transition will generate
a Modem Status Interrupt unless the interrupt has been
disabled by clearing the U1IER[3] bit in the U1IER register.
In auto-cts mode a transition on the CTS1 bit will trigger an
interrupt only if both the U1IER[3] and U1IER[7] bits are
set.
0
0 Disable the CTS interrupt.
1 Enable the CTS interrupt.
8 ABEOIntEn enables the end of auto-baud interrupt. 0
0 Disable End of Auto-baud Interrupt.
1 Enable End of Auto-baud Interrupt.
9 ABTOIntEn enables the auto-baud time-out interrupt. 0
0 Disable Auto-baud Time-out Interrupt.
1 Enable Auto-baud Time-out Interrupt.
31:10 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 401. UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0)
bit description
Bit Symbol Value Description Reset
Value
Table 402. UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only)
bit description
Bit Symbol Value Description Reset
Value
0 IntStatus
0
Interrupt status. Note that U1IIR[0] is active low. The
pending interrupt can be determined by evaluating
U1IIR[3:1]. 1
At least one interrupt is pending.
1 No interrupt is pending.