NXP Semiconductors LPC24XX UM10237 - Manual (Page 95)

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User manual Rev. 04 — 26 August 2009 95 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.25 Static Memory Page Mode Read Delay registers
(EMCStaticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270)
The EMCStaticWaitPage0-3 registers enable you to program the delay for asynchronous
page mode sequential accesses. It is recommended that these registers are modified
during system initialization, or when there are no current or outstanding transactions. This
can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode. This register is accessed with one wait state.
Table 5–93 shows the bit assignments for the EMCStaticWaitPage0-3 registers.
10.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 -
0xFFE0 8214, 234, 254, 274)
The EMCStaticWaitWr0-3 registers enable you to program the delay from the chip select
to the write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode.These registers are not used if the extended wait (EW) bit is enabled in the
EMCStaticConfig register. These registers are accessed with one wait state.
Table 5–94 shows the bit assignments for the EMCStaticWaitWr0-3 registers.
Table 92. Static Memory Read Delay registers (EMCStaticWaitRd0-3 - address 0xFFE0 820C,
0xFFE0 822C, 0xFFE0 824C, 0xFFE0 826C) bit description
Bit Symbol Value Description Reset
Value
4:0 Non-page mode
read wait states
or asynchronous
page mode
readfirst access
wait state
(WAITRD) Non-page mode read or asynchronous page mode read,
first read only: 0x1F
0x0 -
0x1E (n + 1) CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD +
1) x tCCLK.
0x1F 32 CCLK cycles for read accesses (POR reset value).
31:5 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 93. Static Memory Page Mode Read Delay registers0-3 (EMCStaticWaitPage0-3 -
address 0xFFE0 8210, 0xFFE0 8230, 0xFFE0 8250, 0xFFE0 8270) bit description
Bit Symbol Value Description Reset
Value
4:0 Asynchronous
page mode read
after the first
read wait states
(WAITPAGE) Number of wait states for asynchronous page mode read
accesses after the first read: 0x1F
0x0 -
0x1E (n+ 1) CCLK cycle read access time. For asynchronous
page mode read for sequential reads, the wait state time
for page mode accesses after the first read is
(WAITPAGE + 1) x tCCLK.
0x1F 32 CCLK cycle read access time (POR reset value).
31:5 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA