NXP Semiconductors LPC24XX UM10237 - Manual (Page 632)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 632 of 792
1. Basic configuration
The PWM is configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bit PCPWM0/1.
Remark: On reset, the both PWMs are enabled (PCPWM0/1 = 1).
2. Peripheral clock: In the PCLK_SEL0 register ( Table 4–56 ), select PCLK_PWM0/1.
3. Pins: Select PWM pins and pin modes in registers PINSELn and PINMODEn (see
Section 9–5 ).
4. Interrupts: See register PWM0/1MCR ( Table 25–560 ) and PWM0/1CCR
( Table 25–561 ) for match and capture events. Interrupts are enabled in the VIC using
the VICIntEnable register ( Table 7–106 ).
2. Features
• Two PWMs with the same operational features. The PWMs may be operated in a
synchronized fashion by setting them both up to run at the same rate, then enabling
both simultaneously. PWM0 acts as the Master and PWM1 as the slave for this use.
• Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must "release" new match values before they can
become effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
• Three 32 bit capture channels take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt.
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Rev. 04 — 26 August 2009 User manual