NXP Semiconductors LPC24XX UM10237 - Manual (Page 662)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 662 of 792
1. Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate Watchdog reset.
• Programmable 32 bit timer with internal pre-scaler.
• Selectable time period from (T
WDCLK
Ч 256 Ч 4) to (T
WDCLK
Ч 2 32 Ч 4) in multiples of
T
WDCLK
× 4.
• The Watchdog clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock (PCLK, see
Table 4–56 ). This
gives a wide range of potential timing choices for Watchdog operation under different
power reduction conditions. It also provides the ability to run the Watchdog timer from
an entirely internal source that is not dependent on an external crystal and its
associated components and wiring, for increased reliability.
2. Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read
Section 3–3.2 “Reset” on page 31 of this document.
3. Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32 bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
WDCLK
Ч 256 Ч 4)
and the maximum Watchdog interval is (T
WDCLK
Ч 2 32 Ч 4) in multiples of (T
WDCLK
× 4).
The Watchdog should be used in the following manner:
• Set the Watchdog timer constant reload value in WDTC register.
• Setup mode in WDMOD register.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
• Watchdog should be fed again before the Watchdog counter underflows to prevent
reset/interrupt.
UM10237
Chapter 27: LPC24XX WatchDog Timer (WDT)
Rev. 04 — 26 August 2009 User manual