NXP Semiconductors LPC24XX UM10237 - Manual (Page 26)

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User manual Rev. 04 — 26 August 2009 26 of 792
NXP Semiconductors
UM10237
Chapter 2: LPC24XX Memory mapping
7. Prefetch abort and data abort exceptions
The LPC2400 generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regions
are:
• Areas of the memory map that are not implemented for a specific ARM derivative. For
the LPC2400, these are:
– Address space between On-Chip Non-Volatile Memory and the Special Register
space. Labelled "Reserved for On-Chip Memory" in Figure 2–6 .
– Address space between On-Chip Static RAM and the Boot ROM. Labelled
"Reserved Address Space" in Figure 2–6 .
– External Memory
– Reserved regions of the AHB and APB spaces. See Figure 2–7 .
• Unassigned AHB peripheral spaces. See Figure 2–8 .
• Unassigned APB peripheral spaces. See Table 2–17 .
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to
an AHB or APB peripheral address, or to the Special Register space located just below
the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined address
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC2400 documentation and are not a supported feature.
If software executes a write directly to the flash memory, the MAM generates a data abort
exception. Flash programming must be accomplished by using the specified flash
programming interface provided by the Boot Code.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.