11 distributed clocks sync/latch signals, 1 signals, 2 timing specifications – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual
Page 134: Distributed clocks sync/latch signals, Signals, Timing specifications, Table 61: distributed clocks signals, Figure 60: distributed clocks signals, Figure 61: latchsignal timing, Figure 62: syncsignal timing
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