BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 65)

Example Designs
Slave Controller – IP Core for Altera FPGAs III-53
14. Switch over to Quartus II window
15.
Select menu “Project – Add/Remove Files in Project…” and add file
“<IPInst_dir>\example_designs\DBC4CE55_EtherCAT_NIOS\EtherCAT_Demo\mem_init\meminit.
qip
” to project
16. Start compilation (Menu Processing – Start compilation)
17. Download bitstream into FPGA
6.2.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1810 (Altera)/
ET1810 IP Core NIOSII (HW: DBC4CE55)
6.2.5 Downloadable configuration file
An already synthesized time limited OpenCore Plus configuration file
DBC4CE55_EtherCAT_NIOS_time_limited.sof
based on this digital I/O example design can be found in the
<IPInst_dir>\example_designs\DBC4CE55\
folder. After expiration of about 1 hour the design quits its operation unless the JTAG connection to
Quartus remains active. This file must only be used for evaluation purposes, any distribution is not
allowed.