BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 22)

Overview
III-10 Slave Controller – IP Core for Altera FPGAs
Version Release notes
3.0.6
(4/2014) Enhancements:

The Sync/Latch PDI Configuration register 0x0151 shows the same value as
previous IP Core versions. The actual configuration is not affected, since it is fixed
by the IP Core configuration.

Avalon/AXI timing: Quartus might infer an additional clock control buffer into the
on-chip-bus clock signal, causing higher jitter/delay. This clock buffer is now
avoided, leading to better timing results.

Added support for unaligned AXI burst transfers.
Restrictions of previous versions which are removed in this version:

The ERR LED allows overriding using the ERR LED Override register 0x0139
while AL Status register Error Indication bit 0x0130[4] is set. The override flag is
now cleared upon a rising edge of 0x0130[4], and it can be set again afterwards.
Restrictions of this version, which are removed in V3.0.9:

The AXI PDI may not complete an access occasionally if overlapping read and
write accesses occur, causing the processor to wait endlessly.

The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than
the AXI bus width.
Restrictions of this version, which are removed in V3.0.10:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The AXI PDI may write additional bytes to byte lanes without byte enable, if User
RAM (0x0F80:0x0FFF) or Process Data RAM (0x01000 ff.) is written, if the actual
write address on the bus is 32 bit aligned (AWADDR[1:0]=00), and if one or more
of the lower byte enables/byte strobes (WSTRB) is not set.
3.0.9
(9/2014) Enhancements:

The Altera DE2-115 example designs have been updated to support Quartus 14.0
(connected PLL areset signal)
 The PDI watchdog status 0x0110[1] now shows value ‘1’ (watchdog reloaded) if
the PDI watchdog is configured to be not available.

The ESI XML device description does not use special data types anymore.
Restrictions of previous versions which are removed in this version:

The AXI PDI completes accesses if overlapping read and write accesses occur.

The AXI PDI executes read accesses correctly if ARSIZE is smaller than the AXI
bus width.
Restrictions of this version, which are removed in V3.0.10:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The AXI PDI may write additional bytes to byte lanes without byte enable, if User
RAM (0x0F80:0x0FFF) or Process Data RAM (0x01000 ff.) is written, if the actual
write address on the bus is 32 bit aligned (AWADDR[1:0]=00), and if one or more
of the lower byte enables/byte strobes (WSTRB) is not set.