BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 128)

PDI Description
III-116 Slave Controller – IP Core for Altera FPGAs
CLK_PDI_EXT
ADR/BE ADR
READ
BUSY
RD_DATA DATA
t
Read
CS
t Clk
Figure 54: Avalon Read Access (W=1)
CLK_PDI_EXT
ADR/BE ADR
READ
BUSY
RD_DATA DATA0 DATA1 DATA2 DATA3
ADR+1 ADR+3 ADR+2
t Read
CS
t Clk
Figure 55: Avalon Read Access (D=8 Bit, W=4)
CLK_PDI_EXT
ADR/BE ADR
WRITE
BUSY
WR_DATA
ADR+1 ADR+3 ADR+2
DATA0 DATA1 DATA3 DATA2
t Write
CS
t Clk
Figure 56: Avalon Write Access (4 accesses)