BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 48)

IP Core Configuration
III-36 Slave Controller – IP Core for Altera FPGAs
PHY Management Interface
The PHY Management Interface function can be selected or deselected. If it deselected, the other MII
Configuration options are not available.
LINK state and PHY configuration through MI
MI link detection and configuration is available if checked. Ethernet PHYs are configured and link
status is polled via the MII Management Interface. Enhanced link detection has to be activated if MI
link detection and configuration is used and the nMII_LINK0/1/2 signals are not used.
Export PHY address as signals
Enable for dynamically changing PHY addresses (the PHY address configuration is exported as
signals), otherwise the PHY address configuration is static.
Independent PHY addresses
Enable if the PHY addresses are not consecutive. If enabled, the PHY addresses of each port can be
configured individually.
PHY address offset
Configure the base PHY address (belonging to port 0) if the PHY addresses are consecutive.
PHY address port n
Configure the individual PHY address of port n
Tristate Driver inside core (EEPROM/MI)
If selected tri-state drivers of the core are used for access to EEPROM and PHY Management signals.