BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 84)

IP Core Signals
III-72 Slave Controller – IP Core for Altera FPGAs
8.6.4.2 16 Bit µController Interface
Table 32 lists the signals used with a 16 Bit µC PDI.
Table 32: 16 Bit µC PDI
Condition Name Direction Description
Tristate drivers inside
core (µController
configuration)
PDI_uC_DATA[15:0] BIDIR µC data bus
External tristate drivers PDI_uC_DATA_IN[15:0] INPUT µC data bus:
µC  IP Core
PDI_uC_DATA_OUT[15:0] OUTPUT µC data bus:
IP Core  µC
8.6.5 Avalon On-Chip Bus
Table 33 lists the signals used with the Avalon PDI.
Table 33: Avalon PDI
Condition Name Direction Description
Avalon PDI PDI_AVALON_CLK INPUT N*25 MHz Avalon bus clock from
PLL (rising edge of CLK25
synchronous with rising edge of
PDI_AVALON_CLK)
PDI_AVALON_ADR
[18-ld(PDI_EXT_BUS_WIDTH):0] INPUT Avalon address
PDI_AVALON_BE
[PDI_EXT_BUS_WIDTH/8 -1:0] INPUT Avalon byte enable
PDI_AVALON_RD_DATA
[PDI_EXT_BUS_WIDTH -1:0] OUTPUT Avalon slave read data
PDI_AVALON_WR_DATA
[PDI_EXT_BUS_WIDTH:0] INPUT Avalon write data
PDI_AVALON_READ INPUT Avalon read access
PDI_AVALON_WRITE INPUT Avalon write access
PDI_AVALON_CS INPUT Avalon chip select
PDI_AVALON_IRQ OUTPUT Avalon slave interrupt
PDI_AVALON_BUSY OUTPUT Avalon slave busy
PDI_AVALON_SYNC0 OUTPUT DC SYNC0 output. Always 0 if DC
Sync0 is disabled.
PDI_AVALON_SYNC1 OUTPUT DC SYNC1 output. Always 0 if DC
Sync 1 is disabled.
NOTE: If the EtherCAT IP Core is used inside Qsys, PDI_AVALON_SYNC0 and PDI_AVALON_SYNC1 are
declared as interrupt signals for the processor ( valon_ethercat_sync0/1). Use SYNC_OUT0/1 signals for
external use of the SyncSignals.