BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual
Page 140
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Synthesis Constraints
III-128
Slave Controller
– IP Core for Altera FPGAs
set_false_path -from [get_clocks {DIGI_CLK}] -to [get_clocks
{PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {DIGI_CLK}] -to [get_clocks
{PLL_INST|altpll_component|auto_generated|pll1|clk[1]}]
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