BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 61)

Example Designs
Slave Controller – IP Core for Altera FPGAs III-49
6 Example Designs
Example designs are available for:

EBV Cyclone III Evaluation Board DBC3C40 with RMII and 16 bit input/16 bit output Digital I/O

EBV Cyclone IV Evaluation Board DBC4CE55 with RMII and NIOS processor

Altera Cyclone IV DE2-115 Development and Education Board/Industrial Networking Kit (INK) with
MII and NIOS processor

Altera Cyclone IV DE2-115 Development and Education Board/Industrial Networking Kit (INK) with
RGMII and NIOS processor
The EtherCAT master uses an XML file which describes the device and its features. The XML device
description file for all example designs and its schema can be found in the installation directory.
<IPInst_dir>\example_designs\EtherCAT_Device_Description\
Projects have to be compiled and then can be loaded to the configuration devices of the Evaluation
board.
The EtherCAT IP core example design resource consumption figures are based on EtherCAT IP Core
for Altera FPGAs Version 3.0.2 and Altera Quartus II 12.1 SP1.