BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 16)

Overview
III-4 Slave Controller – IP Core for Altera FPGAs
1.4 Target FPGAs
The EtherCAT IP Core for Altera ® FPGAs is targeted at these FPGA families:

Altera Cyclone ® II, Cyclone III, Cyclone III LS, Cyclone IV E+GX, Cyclone V

Altera Cyclone V SoC

Altera Stratix ® , Stratix II, Stratix III, Stratix IV, Stratix V

Altera Arria ® GX, Arria II GX, Arria II GZ, Arria V

Altera Stratix ® GX, Stratix II GX

Intel ® Atom TM Processor E6x5C (formerly Stellarton)

Altera MAX10
The EtherCAT IP Core is designed to support a wide range of FPGAs without modifications, because
it does not instantiate dedicated FPGA resources, or rely on device specific features. Thus, the IP
Core is easily portable to new FPGA families.
The complexity of the IP Core is highly configurable, so its demands for logic resources, memory
blocks, and FPGA speed cover a wide range. Thus, it is not possible to run any IP Core configuration
on any target FPGA with any speed grade. I.e., there are IP Core configurations requiring a faster
speed grade, or a larger FPGA, or even a more powerful FPGA family.
It is necessary to run through the whole synthesis process – including timing checks –, to evaluate if
the selected FPGA is suitable for a certain IP Core configuration before making the decision for the
FPGA. Please consider a security margin for the logic resources to allow for minor enhancements and
bug fixes of the IP Core and the user logic.
1.5 Designflow requirements
For synthesis of the EtherCAT IP Core for Altera FPGAs, at least one of the following Altera Quartus II
versions is needed (with latest service pack):

Altera Quartus II version 13.0

Altera Quartus II version 13.1

Altera Quartus II version 14.0

Altera Quartus II version 14.1
Higher Quartus II versions are probably supported. Installation of the latest service pack is
recommended. A
free version (“Web Edition”) is available from Altera ( http://www.altera.com ).
Optionally for using the EtherCAT IP Core with a NIOS ® based Qsys design, you will need

Altera Nios II Embedded Design Suite