BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 138)

Synthesis Constraints
III-126 Slave Controller – IP Core for Altera FPGAs
Signal Requirement Value Clock reference Description
RGMII_TX_CTL0-3
RGMII_TX_DATA0-
3[3:0] Clock-to-Pin
a) min
b) max
a)
b)
RGMII_TX_CLK
0-2 (both edges) Depending on TX_CLK delay option,
RGMII spec. requirement
Other signals, especially
PDI signals
application dependent