BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 85)

IP Core Signals
Slave Controller – IP Core for Altera FPGAs III-73
8.6.6 AXI3 On-Chip Bus
Table 34 lists the signals used with the AXI3 PDI.
Table 34: AXI3 PDI
Condition Name Direction Description
AXI3 PDI PDI_AXI_AWID
[PDI_BUS_ID_WIDTH-1:0] INPUT Write address ID
PDI_AXI_AWADDR[15:0] INPUT Write address
PDI_AXI3_AWLEN[3:0] INPUT Write length
PDI_AXI_AWSIZE[2:0] INPUT Write size
PDI_AXI_AWBURST[1:0] INPUT Write burst type
PDI_AXI3_AWLOCK INPUT Write lock
PDI_AXI_AWCACHE[3:0] INPUT Write cache type
PDI_AXI_AWPROT[2:0] INPUT Write protection type
PDI_AXI_AWVALID INPUT Write address valid
PDI_AXI_AWREADY OUTPUT Write address ready
PDI_AXI_WID[PDI_BUS_ID_WIDTH-1:0] INPUT Write data ID
PDI_AXI_WDATA
[PDI_EXT_BUS_WIDTH-1:0] INPUT Write data
PDI_AXI_WSTRB
[PDI_EXT_BUS_WIDTH/8-1:0] INPUT Write data byte enable
PDI_AXI_WLAST INPUT Write data last
PDI_AXI_WVALID INPUT Write data valid
PDI_AXI_WREADY OUTPUT Write data ready
PDI_AXI_BID[PDI_BUS_ID_WIDTH-1:0] OUTPUT Write response ID
PDI_AXI_BRESP[1:0] OUTPUT Write response
PDI_AXI_BVALID OUTPUT Write response valid
PDI_AXI_BREADY INPUT Write response ready
PDI_AXI_ARID[PDI_BUS_ID_WIDTH-1:0] INPUT Read address ID
PDI_AXI_ARADDR[15:0] INPUT Read address
PDI_AXI3_ARLEN[3:0] INPUT Read length
PDI_AXI_ARSIZE[2:0] INPUT Read size
PDI_AXI_ARBURST[1:0] INPUT Read burst type
PDI_AXI3_ARLOCK INPUT Read lock
PDI_AXI_ARCACHE[3:0] INPUT Read cache type
PDI_AXI_ARPROT[2:0] INPUT Read protection type
PDI_AXI_ARVALID INPUT Read address valid
PDI_AXI_ARREADY OUTPUT Read address ready
PDI_AXI_RID
[PDI_BUS_ID_WIDTH-1:0] OUTPUT Read data ID
PDI_AXI_RDATA
[PDI_EXT_BUS_WIDTH-1:0] OUTPUT Read data
PDI_AXI_RRESP[1:0] OUTPUT Read response
PDI_AXI_RLAST OUTPUT Read data last
PDI_AXI_RVALID OUTPUT Read data valid
PDI_AXI_RREADY INPUT Read data ready
PDI_AXI_IRQ_MAIN OUTPUT Interrupt