BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 104)

PDI Description
III-92 Slave Controller – IP Core for Altera FPGAs
SOF
DATA Input DATA
t
SOF_to_DATA_setup
t
SOF
t
SOF_to_DATA_hold
Figure 35: Digital Input: Input data sampled at SOF, I/O can be read in the same frame
LATCH_IN
DATA Input DATA
t DATA_hold t DATA_setup
t
LATCH_IN
t
Input_event_delay
Figure 36: Digital Input: Input data sampled with LATCH_IN
SYNC0/1
DATA Input DATA
t
DATA_hold
t
DATA _set up
t
Input_event_delay
Figure 37: Digital Input: Input data sampled with SYNC0/1