BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 62)

Example Designs
III-50 Slave Controller – IP Core for Altera FPGAs
6.1 EBV Cyclone III DBC3C40 with Digital I/O
6.1.1 Configuration and resource consumption
Table 13: Resource consumption Digital I/O example design DBC3C40
Configuration Resources EP3C40
Physical layer 2x RMII Les 8,626 22 %
Internal Function 2x FMMU
4x SyncManager
1 KB RAM Registers 4,120 10 %
Distributed clocks none M9K 2 2 %
Feature details RUN_LED,
LED Test PLLs 1 25 %
PDI Digital I/O: 2 Byte IN, 2
Byte OUT Multiplier
elements 0 0 %
NOTE: The board uses two individual PHY management interfaces, with both PHYs having the same PHY
addresses. Additionally, some of the PHY address bits have to be configured by extra logic inside the FPGA.
Because of the identical PHY addresses, the management interfaces on the board cannot be combined to one,
and thus, the EtherCAT IP Core cannot make use of the MII management interfaces of the PHY.
The Ethernet PHYs used on the DBC3C40 require Enhanced link detection for proper link loss reaction times.
Due to the hardware restrictions, it cannot be enabled on this board. This is suitable for evaluation purposes, but
not for production.
It is probably possible to change the PHY addresses on the board, combine the two management interfaces
inside the FPGA and add extra logic for proper configuration of the PHY address bits which are strapped on
signals connected to the FPGA. If this can be done, the PHY management interface as well as the Enhanced Link
Detection should be enabled.
6.1.2 Functionality
Functionality of the Digital I/O example design:

Digital input data from the buttons and the joystick is available in the Process Data RAM
(0x1000:0x1001).

Digital output data from Digital Output register (0x0F00:0x0F01) is visualized with IO LEDs.
6.1.3 Implementation
The EtherCAT IP Core MegaFunction needs to be completed before implementing the example
design (copy library files to the project folder). Perform the following steps for implementation:
1. Open Altera Quartus II
2. Open example design from <IPInst_dir>\example_designs\DBC3C40_EtherCAT_DIGI
3. Open MegaWizard Plug-
In Manager, select “Edit and existing custom megafunction variation”
4. Select “ethercat_digitalio.vhd”
5. In the MegaWizard, select Finish. This will complete the EtherCAT IP Core MegaFunction.
6. Start compilation (Menu Processing
– Start compilation).
7. Download bitstream into FPGA
6.1.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1810 (Altera)/
ET1810 IP Core 16 Ch. Dig. In-/Output (HW: DBC3C40)